This invention relates generally to differential amplifiers and, more particularly, to a differential amplifier including first and second differential input transistors wherein a balanced RC gain reduction network is coupled between the collectors of the input transistors so as to create a symmetrical parasitic capacitance.
U.S. patent application Ser. No. 880,251 filed 6/30/86 entitled AMPLIFIER HAVING IMPROVED GAIN-BANDWIDTH PRODUCT and filed of even date herewith disloses an amplifier wherein a series RC network is coupled between the collectors of the differential input transistors so as to provide a gain reduction and therefore improve the gain bandwidth product. Unfortunately, the inclusion of such an RC network produces an undesirable parasitic capacitance on one side of the amplifier thus producing nonsymmetrical loading on the amplifier and destroying its balanced state. This is undesirable for several reasons. For example, the parasitic capacitance (C.sub.S) on one side of the amplifier will cause the AC gain of that side to roll off with frequency relative to the other side. Additionally, a one sided parasitic capacitance will cause any symmetrical base-collector signals to produce an unwanted differential signal across the collectors which is supplied to the second stage and amplified thereby.